1. Field of the Invention
The present invention relates to semiconductor elements, in particular, semiconductor power switching elements for controlling an inverter or the like.
2. Description of the Prior Art
A conventional semiconductor power switching element will be described with reference to FIG. 11. For a semiconductor element formed of a silicon semiconductor shown in FIG. 11, a silicon semiconductor in which an n-type epitaxial growth layer 112 is formed on an n+-type silicon substrate 111 is used. P-type semiconductor regions 113 are formed in a surface of the n-type epitaxial growth layer 112, and n+-type semiconductor regions 114 serving as a source region are formed in the p-type regions. As electrodes, a source electrode 119 is formed so as to be in contact with the n+-type region 114 and a gate electrode 118 is formed via an insulating layer 116 that is formed by oxidation. Furthermore, a drain electrode 117 is provided on a back surface. In a vertical insulated gate field-effect transistor (vertical MOSFET) that is formed in this manner, when a bias voltage is applied to the gate electrode 118, an inversion layer is produced in the surface layer of the p-type region 113 that is immediately below the gate electrode.
In this semiconductor element, the source electrode 119 also is in contact with the p-type regions 113 to set the electric potential of the p-type region 113. Therefore, a parasitic diode with a p-type source and an n-type drain exists between the source and the drain of the transistor.
In a semiconductor element formed of a silicon carbide (SiC) semiconductor shown in FIG. 12, a vertical MOSFET having a so-called trench structure is formed. In this semiconductor element, silicon carbide is used where an n-type epitaxial growth layer 122 and a p-type epitaxial growth layer 123 are formed in this order on an n+-type silicon carbide substrate 121. N+-type semiconductor regions 124 to serve as source regions are formed in the surface of the p-type layer 123. A recess penetrating the p-type layer 123 is formed in the n+-type region 124 by photolithography and etching to achieve a trench structure. A gate electrode 128 is provided on the surface of the recess via an insulating film 126 formed by oxidation. In the thus formed silicon carbide MOSFET having a trench structure, when a bias voltage is applied to the gate electrode 128, an inversion layer (channel) is produced in the p-type region 123 that is in contact with the trench wall surface. This element is disclosed, for example, in Silicon Carbide; A review of Fundamental Questions and Applications, edited by W. J. Choyke, H. Matsunami, and G. Pensl, Akademie Verlag 1997, Vol. II, pp. 369-388.
In this semiconductor element, for the same reason as above, since the source electrode 129 is in contact with the p-type layer 123, a parasitic diode with a p-type source and an n-type drain exists between the source and the drain.
In these semiconductor elements, a parasitic diode exists between the source and the drain, as described above, and therefore, when the semiconductor element is switched off, a delay by the amount of time required for reverse recovery of the parasitic diode occurs. This delay is caused by the fact that the pin junction continues to be on even after the semiconductor element is switched off because of the presence of minority carriers injected to the layers constituting the parasitic diode while the semiconductor element is on. Furthermore, current that has flowed until the p/n junction is no longer on constitutes a switching loss.
A semiconductor element that can solve the above-described problem involved in the production of the parasitic diode has been proposed (JP 9 (1997)-55507 A). As shown in FIG. 13, this semiconductor element is provided with a Schottky diode region adjacent to a region in which the same MOSFET as in FIG. 11 is formed. Reference numerals in FIG. 13 are the same as those shown in FIG. 11. In this Schottky diode region, the electrode 119 serving as the source electrode in the MOSFET region forms a Schottky junction with the n-type layer 112. If the Schottky diode is provided parallel to the parasitic diode in this manner, the reverse recovery time due to minority carriers can be reduced.
In the semiconductor element shown in FIG. 13, the Schottky diode is surrounded by a p-type circular guard ring region 121 to ensure the breakdown voltage. With this, an n+-type channel stopper region 122 is further provided between the p-type region 113 and the p-type guard ring region 121.
With the semiconductor element of FIG. 13, when the Schottky diode region is provided, the element area is increased. The increase of the element area is detrimental to the compactness of the semiconductor element. This element attempts to improve the breakdown voltage of the Schottky diode by using the guard ring region 121 in the periphery of the Schottky diode having a relatively smaller breakdown voltage than that of a transistor. However, the presence of the further provided guard ring region 121 or the channel stopper region 122 increases the element area up to about 200%.
In the semiconductor element shown in FIG. 13 as well as in the semiconductor element shown in FIG. 11, it is advantageous that the distance d (FIG. 11) between adjacent p-type layers 113 is larger to let a large current flow. However, when the distance d is increased, depletion layers 115 (FIG. 11) due to the p/n junction are not overlapped, or even if they are overlapped, the thickness of the depletion layer is not sufficient in the vicinity of the center of the distance. Therefore, when it is attempted to increase the current capacity by increasing the distance d, all the voltage between the gate electrode 118 and the drain electrode 117 is applied substantially to the insulating film 116, so that this insulating film becomes susceptible to breakdown. Thus, in the semiconductor power switching element, in particular, when producing an element suitable for a large current, it is an important issue to ensure the breakdown voltage.